1. Technical Field
This disclosure relates to semiconductor testing, and more particularly, to a method for increasing test throughput by providing a method for increasing test speeds of semiconductor test equipment.
2. Description of the Related Art
Semiconductor devices, especially memory devices, are typically tested by generating a pattern of inputs and transferring the pattern of inputs to the array of memory cells. The data written to the memory cells is then retrieved and compared to the input pattern to identify abnormalities or failures. The failures of the cells are stored in a tester in an address failure memory and correlated to repair the failures by replacing failed cells with redundancies.
In typical set ups, a complete test sequence is run on the tester to identify failures, which are stored in an address fail memory, and perform redundancy calculations. In addition, semiconductor testers include several modules or devices. Among these are a pattern generator, a scrambler, a probe card and socket file. These devices provide different testing configurations and patterns for testing semiconductor wafer components. Wafer testers are typically run by a master program. The master program coordinates all testing functions and modules by setting appropriate parameters for different modules or programs for the wafer tester.
During a test, a device under test (DUT) is coupled to the tester. Testers and probe cards as well as other test equipment tend to be rather large in comparison to the wafers or chips to be tested (DUT). As such, relatively large distances through the test equipment must be overcome to test the DUT. This distance results in delays, which reduce throughput and increase test time.
Therefore, a need exists for a method for testing semiconductor devices, which increases test speed and test throughput.
A method for testing semiconductor memories, in accordance with the invention includes providing a tester having a plurality of data channels. The tester operates at a first clock rate. A memory device to be tested is included with a plurality of data ports connected to the data channels. The memory device has a data compression circuit for compressing test data such that a number of the plurality of data ports are available for other functions. Data is transferred between the memory device and the tester at a rate higher than the first clock rate by employing the plurality of data ports including the number of the plurality of data ports, such that the memory device operates at the higher rate and the tester operates at the first rate. In other embodiments data ports are made available by employing an on-chip addressing method. In other embodiments, an on-chip clock receiver provides double data rate clocking of the memory device.
In other methods, the data compression circuit compresses data with a ratio of 4 to 1. The step of transferring data may include the step of transferring data in an order such that address information is conveyed by a position of the data. The memory device may include an internal clock, and the method may further include the step of operating the memory device clock to provide the higher rate for transferring data to and from the tester. The method may include the step of dividing clock cycles of the internal clock to provide the higher rate. The higher rate is preferably an integer multiple of the first rate. The integer multiple may be determined by a burst length of the memory device. The method may further include the steps of supplying the first clock rate to the memory device from the tester and doubling an internal clock rate of the memory device by employing rising and falling edges of the external clock cycle. The method may include the step of dividing the internal clock rate of the memory device to further increase the internal clock rate.
Another method for testing semiconductor memories, in accordance with the present invention, includes providing a tester having a plurality of data channels. The tester operates at a first clock rate. A memory device to be tested is provided and includes a plurality of data ports and a plurality of addressing ports connected to the data channels. The memory device includes an address register for generating addresses on the memory device such that a number of the plurality of address ports employed for addressing are available for other functions. Data is transferred between the memory device and the tester at a rate higher than the first clock rate by employing the plurality of data ports and address ports, such that the memory device operates at the higher rate and the tester operates at the first rate.
In other methods, the step of generating addresses in the address register based on a number of clock cycles is included. The step of transferring data may include the step of transferring data in an order such that address information is conveyed by a position of the data. The memory device may include an internal clock, and the method may further include the step of operating the memory device clock to provide the higher rate for transferring data to and from the tester. The method may include the step of dividing clock cycles of the internal clock to provide the higher rate. The higher rate is preferably an integer multiple of the first rate, and the integer multiple may be determined by a burst length of the memory device. The method may further include the steps of supplying the first clock rate to the memory device from the tester and doubling an internal clock rate of the memory device by employing rising and falling edges of the external clock cycle. The method may include the step of dividing the internal clock rate of the memory device to further increase the internal clock rate.